Cadence Supports TSMC Reference Flow 6.0 to Accelerate 65-Nanometer Design
Design Platforms Address Power Optimization, Design for
Manufacturing (DFM), Chip-Package Integration, and Design
for Test (DFT) Challenges
SAN JOSE, Calif.—(BUSINESS WIRE)—June 9, 2005—
Cadence Design Systems, Inc. (NYSE:CDN) (Nasdaq:CDN) and Taiwan
Semiconductor Manufacturing Company (NYSE:TSM) today announced the
integration of the Cadence(R) Encounter(TM) digital IC design platform
and Cadence Allegro(R) system interconnect platform into TSMC's
Reference Flow 6.0. This reference flow, which supports designs
targeting TSMC's Nexsys(SM) 65-nanometer, process technologies,
includes innovative Cadence software for power optimization and
analysis, design for manufacturing (DFM), chip-package integration,
and design for test (DFT).
This latest milestone in the ongoing design chain collaboration
between the two companies delivers an RTL-to-package reference flow to
accelerate time-to-volume for high-performance designs and low-power
designs. It delivers a comprehensive methodology to address complex
design issues at 90 and 65 nanometers, such as tight manufacturing
parameters, an exponential increase in leakage power, and new
extraction requirements. Within Reference Flow 6.0, Cadence
technologies address these key issues by performing concurrent routing
and dual via insertion, supporting aggressive leakage power reduction
strategies and optimizing package performance and cost.
"Reference Flow 6.0's Cadence track incorporates Cadence
technologies to lower the entry barrier for designers targeting TSMC's
advanced processes," said Ed Wan, senior director of design service
marketing at TSMC. "We collaborated closely with Cadence to meet the
complex requirements that designers are facing at 65 nanometers, which
include power management, chip and package co-design, and
manufacturing."
"Our collaboration with leaders throughout the design chain
provides silicon-validated design solutions necessary for market
success," said Pankaj Mayor, group director of business development
for Industry Alliances at Cadence. "We focus on correlating models,
software and IP with silicon by creating test chips such as the
low-power test chip with TSMC through the Silicon Design Chain
Initiative earlier this year. Leveraging those results through TSMC
Reference Flow 6.0 improves the probability of nanometer design
success."
Power Optimization and Analysis
TSMC Reference Flow 6.0 incorporates key elements of the Cadence
Encounter platform -- voltage domain-aware technologies from Reference
Flow 5.0 -- to create power-gated paths and dynamic voltage scaling.
Designers can use these technologies to design with multiple supply
voltages and power domains, leakage power and de-coupling capacitance
optimization, automatic power grid generation, and dynamic voltage
(IR) drop analysis with actual IC package load models. The Encounter
platform provides a scalable methodology to go from a non-power domain
design to power domain-based designs.
Elements of the Encounter platform within Reference Flow 6.0
include Encounter RTL Compiler global synthesis, Encounter Test, SoC
Encounter Global Physical Synthesis (GPS), Cadence extraction
technology, VoltageStorm(R) Dynamic Gate power rail analysis, and
CeltIC(R) Nanometer Delay Calculator (NDC), which work together to
deliver high quality of silicon (QoS), improved timing closure, and
reduced area.
DFM
Cadence SoC Encounter Global Physical Synthesis (GPS), which is
included in Reference Flow 6.0, brings to the IC design process
critical manufacturing issues such as wire spreading, double-cut via
optimization, and metal fill. SoC Encounter GPS can automatically
insert metal fill into a placed and routed design to achieve a metal
density within the range recommended by TSMC design rules. It also
enables automated wire-spreading and double-cut (dual) via insertion,
which positively impact yield.
Chip-Package Co-Design
Routability, timing, and IR drop are major concerns for chip and
package co-design and integration. To help optimize chip and package
design flows, TSMC features the Cadence Allegro system interconnect
platform in Reference Flow 6.0. Allegro Package Designer can help
achieve design of high-performance interconnect across the IC,
package, and PCB domains. The Allegro platform comprises a common
constraint-driven flow across design entry, including extraction of
package parasitics and inclusion of these package effects into the
IC-level timing and static and dynamic IR drop modeling environments.
Within TSMC Reference Flow 6.0, the Allegro platform addresses 65
nanometers and below design challenges, such as flip-chip interconnect
density, gigahertz signal integrity and clean power delivery of
low-voltage, high power consumption chips.
DFT and True-Time Delay Test
Encounter Test has been validated by TSMC in Reference Flow 6.0 to
address DFT and delay test ATPG. Increasing design complexity and
nanometer-scale geometries make manufacturing test critical for IC
success. Creating an effective, full-chip test architecture,
minimizing test cost, maximizing product quality, and quickly ramping
yield are major design challenges. Encounter Test addresses these
issues within the TSMC reference flow with the industry's most
advanced, comprehensive test solution, including DFT, delay test,
compression and diagnostics.
Availability
TSMC Reference Flow 6.0, through the Company's customer web site,
TSMC Online (http://online.tsmc.com/), or by contacting any TSMC
account manager.
About TSMC
TSMC is the world's largest dedicated semiconductor foundry,
providing the industry's leading process technology and the foundry
industry's largest portfolio of process-proven library, IP, design
tools and reference flows. The company operates two advanced
twelve-inch wafer fabs, five eight-inch fabs and one six-inch wafer
fab. TSMC also has substantial capacity commitments at its
wholly-owned subsidiary, WaferTech and TSMC (Shanghai), and its joint
venture fab, SSMC. In early 2001, TSMC became the first IC
manufacturer to announce a 90-nm technology alignment program with its
customers. TSMC's corporate headquarters are in Hsinchu, Taiwan. For
more information about TSMC please see http://www.tsmc.com.
About Cadence
Cadence enables global electronic-design innovation and plays an
essential role in the creation of today's integrated circuits and
electronics. Customers use Cadence software and hardware,
methodologies, and services to design and verify advanced
semiconductors, consumer electronics, networking and
telecommunications equipment, and computer systems. Cadence reported
2004 revenues of approximately $1.2 billion, and has approximately
4,700 employees. The company is headquartered in San Jose, Calif.,
with sales offices, design centers, and research facilities around the
world to serve the global electronics industry. More information about
the company, its products, and services is available at
www.cadence.com.
Cadence, the Cadence logo, Allegro, CeltIC, and VoltageStorm are
registered trademarks and Encounter is a trademark of Cadence Design
Systems, Inc. All other trademarks are the property of their
respective owners.
Contact:
Cadence Design Systems, Inc.
Bruce Chan, 408-894-2961
Email Contact
or
TSMC North America
Dan Holden, 408-382-7921
Cell: 408-910-1141
Email Contact
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